This invention relates to integrated circuits such as programmable logic device integrated circuits, and more particularly, to programmable logic device integrated circuits with dynamic phase alignment circuits.
Programmable logic devices are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design tools to design a custom logic circuit. When the design process is complete, the tools generate configuration data. The configuration data is loaded into a programmable logic device to configure the device to perform the functions of the custom logic circuit.
In a typical system, a programmable logic device integrated circuit and other integrated circuits are mounted on a circuit board. The circuit board contains conductive paths that interconnect the integrated circuits. A system may also have paths that interconnect integrated circuits on different boards. Programmable logic devices contain transceiver circuitry for transmitting and receiving data over these communications paths.
Programmable logic device transceiver circuitry includes input and output drivers. The input and output drivers may use differential signaling schemes in which a pair of signals are referenced to each other or single-ended signaling schemes in which signals are referenced to ground. In high-speed environments, the input and output drivers are generally differential drivers and handle differential signals.
In source-synchronous system architectures, multiple transmitters share a common clock. Each transmitter may transmit data signals and a clock signal over a respective bus. A programmable logic device may receive and process the signals on each bus. With conventional arrangements, programmable logic devices use numerous phase-locked-loop circuits to receive and process the data transmitted over the buses.
It would be desirable to be able to provide integrated circuits such as programmable logic device integrated circuits with transceiver circuitry that handles source-synchronous transmissions while making efficient use of on-chip resources such as phase-locked-loop circuits.